TY - JOUR
T1 - New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell
AU - Momodomi, M.
AU - Kirisawa, R.
AU - Nakayama, R.
AU - Aritome, S.
AU - Endoh, T.
AU - Itoh, Y.
AU - Iwata, Y.
AU - Oodaira, H.
AU - Tanaka, T.
AU - Chiba, M.
AU - Shirota, R.
AU - Masuoka, F.
PY - 1988/12
Y1 - 1988/12
N2 - Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0-μm design rules, the unit cell area per bit is 12.9 μm2, which is small enough to realize a 4-Mb EEPROM.
AB - Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0-μm design rules, the unit cell area per bit is 12.9 μm2, which is small enough to realize a 4-Mb EEPROM.
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M3 - Conference article
AN - SCOPUS:0024176887
SN - 0163-1918
SP - 412
EP - 415
JO - Technical Digest - International Electron Devices Meeting
JF - Technical Digest - International Electron Devices Meeting
T2 - Technical Digest - International Electron Devices Meeting 1988
Y2 - 11 December 1988 through 14 December 1988
ER -