@inproceedings{e7af5c7fe32a4ca0bf08dc079a06f08c,
title = "New multichip-to-wafer 3D integration technology using Self-Assembly and Cu nano-pillar hybrid bonding",
abstract = "New 3D integration technology using self-assembly and Cu nano-pillar hybrid bonding are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled with a high alignment accuracy making use of liquid surface tension in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier and electrostatically bonded by applying a voltage to bipolar electrodes on the SAE carrier. The self-assembled dies on the carrier are simultaneously transferred to another wafer or interposer wafer by electrostatically debonding the carrier wafer after Cu nano-pillar hybrid bonding of self-assembled dies.",
author = "M. Koyanagi and Lee, {K. W.} and T. Fukushima and T. Tanaka",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 ; Conference date: 25-10-2016 Through 28-10-2016",
year = "2016",
doi = "10.1109/ICSICT.2016.7998914",
language = "English",
series = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "338--341",
editor = "Ru Huang and Ting-Ao Tang and Yu-Long Jiang",
booktitle = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",
address = "United States",
}