TY - GEN
T1 - New three dimensional (3D) memory array architecture for future ultra high density DRAM
AU - Endoh, T.
AU - Sakuraba, H.
AU - Shinmei, K.
AU - Masuoka, F.
PY - 1999
Y1 - 1999
N2 - Three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM, when one bit-line has 1K-bit cells and the same design rules are used. Moreover, array area of 1M-bit DRAM using the proposed architecture, is reduced to 11.5% of normal DRAM using the same design rules.
AB - Three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM, when one bit-line has 1K-bit cells and the same design rules are used. Moreover, array area of 1M-bit DRAM using the proposed architecture, is reduced to 11.5% of normal DRAM using the same design rules.
UR - http://www.scopus.com/inward/record.url?scp=0033298036&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033298036&partnerID=8YFLogxK
U2 - 10.1109/icmel.2000.838729
DO - 10.1109/icmel.2000.838729
M3 - Conference contribution
AN - SCOPUS:0033298036
SN - 0780352351
SN - 9780780352353
T3 - 2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
SP - 447
EP - 450
BT - 2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
PB - IEEE
T2 - 22nd International Conference on Microelectronics (MIEL 2000)
Y2 - 14 May 2000 through 17 May 2000
ER -