New three-dimensional high-density stacked-surrounding gate transistor (S-SGT) flash memory architecture using self-aligned interconnection fabrication technology without photolithography process for tera-bits and beyond

New three-dimensional Stacked-Surrounding Gate Transistor (S-SGT) flash memory architecture can achieve the cell area of 3.88F² per bit using the 0.2μm design rule. The new architecture is realized by stacking two select transistors and two memory cells vertically on each pillar located in a two-dimensional array matrix. Each gate and each interconnection of this new architecture are fabricated by the vertical self-alignment process and horizontal self-alignment process simultaneously using HTO conformal deposition and reactive ion etching (RIE) without using the photolithography process. The new three-dimensional S-SGT flash memory architecture is applicable to high-density nonvolatile memories as large as tera-bits and beyond.