TY - GEN
T1 - New three-dimensional integration technology to achieve a super chip
AU - Koyanagi, Mitsumasa
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
PY - 2006
Y1 - 2006
N2 - We have proposed a new mree-dimensional (3D) integration technology based on a chip-to-wafer bonding method which is called a super chip integration technology. Various kinds of chips such as processor chip, memory chips, analog IC chip and sensor chips which are fabricated by different technologies can be vertically stacked into a 3D LSI chip by using a super chip integration technology. Such 3D LSI chip is called a super chip. Various kinds of chips with different chip size, chip thickness and material can be vertically stacked in the super chip integration technology. To establish the super chip integration technology, several key technologies of vertical interconnection formation, chip alignment and bonding, adhesive injection, and chip thinning and planarization were developed. By using the super chip integration technology, three-layer stacked LSI chips with vertical interconnections were successfully fabricated.
AB - We have proposed a new mree-dimensional (3D) integration technology based on a chip-to-wafer bonding method which is called a super chip integration technology. Various kinds of chips such as processor chip, memory chips, analog IC chip and sensor chips which are fabricated by different technologies can be vertically stacked into a 3D LSI chip by using a super chip integration technology. Such 3D LSI chip is called a super chip. Various kinds of chips with different chip size, chip thickness and material can be vertically stacked in the super chip integration technology. To establish the super chip integration technology, several key technologies of vertical interconnection formation, chip alignment and bonding, adhesive injection, and chip thinning and planarization were developed. By using the super chip integration technology, three-layer stacked LSI chips with vertical interconnections were successfully fabricated.
UR - http://www.scopus.com/inward/record.url?scp=34547247536&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34547247536&partnerID=8YFLogxK
U2 - 10.1109/ICSICT.2006.306217
DO - 10.1109/ICSICT.2006.306217
M3 - Conference contribution
AN - SCOPUS:34547247536
SN - 1424401615
SN - 9781424401611
T3 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
SP - 318
EP - 321
BT - ICSICT-2006
PB - IEEE Computer Society
T2 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Y2 - 23 October 2006 through 26 October 2006
ER -