Nonvolatile field-programmable gate array using 2-transistor-1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic

A dynamically reconfigurable nonvolatile field-programmable gate array (FPGA) with a multi-context (MC) cell array structure that uses threeterminal magnetic tunnel junction (MTJ) devices is proposed. The use of single-ended circuitry together with a 2-transistor and 1-MTJ (2T-1MTJ) context cell allows for the minimization of the area overhead of the context array with nonvolatile storage capability. As the 2T-1MTJ cell has no power line, the leakage current overhead is also minimized. With the proposed implementation, the transistor counts and leakage power during power-on are reduced by 59 and 71%, respectively, compared to the static random-access memory (SRAM)-based implementation using 40-nm CMOS technology.