Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction

Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu

doi:10.1109/JSSC.2014.2362853

Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Research output: Contribution to journal › Article › peer-review

53 Citations (Scopus)

Abstract

A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.

Original language	English
Article number	6942275
Pages (from-to)	476-489
Number of pages	14
Journal	IEEE Journal of Solid-State Circuits
Volume	50
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.2014.2362853
Publication status	Published - 2015 Feb 1

Keywords

Automated design environment
magnetic tunnel junction (MTJ)
motion-vector prediction
nonvolatile logic-in-memory (NV-LIM)
power gating
spin-transfer torque random access memory (STT-RAM)

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2014.2362853

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Natsui, M., Suzuki, D., Sakimura, N., Nebashi, R., Tsuji, Y., Morioka, A., Sugibayashi, T., Miura, S., Honjo, H., Kinoshita, K., Ikeda, S., Endoh, T., Ohno, H., & Hanyu, T. (2015). Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction. IEEE Journal of Solid-State Circuits, 50(2), 476-489. [6942275]. https://doi.org/10.1109/JSSC.2014.2362853

Natsui, M, Suzuki, D, Sakimura, N, Nebashi, R, Tsuji, Y, Morioka, A, Sugibayashi, T, Miura, S , Honjo, H, Kinoshita, K, Ikeda, S , Endoh, T , Ohno, H & Hanyu, T 2015, 'Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction', IEEE Journal of Solid-State Circuits, vol. 50, no. 2, 6942275, pp. 476-489. https://doi.org/10.1109/JSSC.2014.2362853

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abstract = "A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.",

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AU - Sugibayashi, Tadahiko

AU - Miura, Sadahiko

AU - Honjo, Hiroaki

AU - Kinoshita, Keizo

AU - Ikeda, Shoji

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AB - A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.

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Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction

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Keywords

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