TY - JOUR
T1 - Nonvolatile low power 16-bit/32-bit magnetic tunnel junction based binary counter and its scaling
AU - Togashi, Shuta
AU - Ohsawa, Takashi
AU - Endoh, Tetsuo
PY - 2012/2
Y1 - 2012/2
N2 - We propose a nonvolatile 16-bit/32-bit magnetic tunnel junction (MTJ) based binary counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-bit/32-bit counter is 59.1 and 72.5% smaller in case of 45 and 16nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) counter at low frequency (100 Hz). The proposed nonvolatile 32-bit counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16nm node, respectively, in comparison with the conventional CMOS counter. Moreover, we propose a hybrid 32-bit counter that is constructed with CMOS counter units for the beginning stages and nonvolatile MTJ based counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS counter for 16nm node. As a result, clear scalability of the proposed MTJ based multi-bit counter is obtained from the viewpoint of suppressing power.
AB - We propose a nonvolatile 16-bit/32-bit magnetic tunnel junction (MTJ) based binary counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-bit/32-bit counter is 59.1 and 72.5% smaller in case of 45 and 16nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) counter at low frequency (100 Hz). The proposed nonvolatile 32-bit counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16nm node, respectively, in comparison with the conventional CMOS counter. Moreover, we propose a hybrid 32-bit counter that is constructed with CMOS counter units for the beginning stages and nonvolatile MTJ based counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS counter for 16nm node. As a result, clear scalability of the proposed MTJ based multi-bit counter is obtained from the viewpoint of suppressing power.
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U2 - 10.1143/JJAP.51.02BE07
DO - 10.1143/JJAP.51.02BE07
M3 - Article
AN - SCOPUS:84857477870
SN - 0021-4922
VL - 51
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
IS - 2 PART 2
M1 - 02BE07
ER -