TY - GEN
T1 - Novel switch block architecture using non-volatile functional pass-gate for multi-context FPGAs
AU - Hariyama, Masanori
AU - Chong, Weisheng
AU - Ogata, Sho
AU - Kameyama, Michitaka
PY - 2005
Y1 - 2005
N2 - Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One of typical DPGA architectures is a multi-context one. Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained reconfigurable architecture called reconfigurable context memory (RCM) is presented based on the fact that there are redundancy and regularity in configuration bits between different contexts. A floating-MOS functional pass-gate, where storage and switch functions are merged, is used to construct the RCM area-efficiently.
AB - Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One of typical DPGA architectures is a multi-context one. Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained reconfigurable architecture called reconfigurable context memory (RCM) is presented based on the fact that there are redundancy and regularity in configuration bits between different contexts. A floating-MOS functional pass-gate, where storage and switch functions are merged, is used to construct the RCM area-efficiently.
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U2 - 10.1109/ISVLSI.2005.52
DO - 10.1109/ISVLSI.2005.52
M3 - Conference contribution
AN - SCOPUS:26844469775
SN - 076952365X
SN - 9780769523651
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI
SP - 46
EP - 50
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
A2 - Smailagic, A.
A2 - Ranganathan, N.
T2 - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Y2 - 11 May 2005 through 12 May 2005
ER -