Novel switch-block architecture using reconfigurable context memory for multi-context FPGAs

Dynamically-programmable gate arrays (DPGAs) promise lower cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One of typical DPGA architectures is a multi-context one. Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. Especially, switch blocks require a much larger memory capacity than look-up tables. This paper proposes a novel switch block architecture that can greatly reduce the overhead of the context memory in MC-FPGAs. A fine-grained reconfigurable architecture for switch blocks is presented based on the fact that there are redundancy and regularity in configuration bits between different contexts. Under a constraint of the same number of contexts, an area of the proposed switch block is 59% of that of the conventional switch block.