Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

Tetsuo Endoh, Kazushi Kinoshita, Takuji Tanigami, Yoshihisa Wada, Kota Sato, Kazuya Yamada, Takashi Yokoyama, Noburo Takeuchi, Kenichi Tanaka, Nobuyoshi Awaya, Keizou Sakiyama, Fujio Masuoka

Research output: Contribution to journalArticlepeer-review

45 Citations (Scopus)


In order to overcome the limitation of cell area of 4F2 per bit in conventional NAND Flash Memory cells, Stacked-Surrounding Gate Transistor (S-SGT) structured cell is proposed. The new structured cell achieves cell area of 4F2/N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multi bit per memory cell technology. The S-SGT structured cell consisting of 2 stacked memory cells in one silicon pillar achieves cell area per bit less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2μm design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, the same as conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories as large as 16G/64G bit Flash Memory or beyond.

Original languageEnglish
Pages (from-to)33-36
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2001 Jan 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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