NPN 30 GHz, 32 GHz fT complementary bipolar technology

Takahiro Onai; Eiji Ohue; Yohji Idei; Masamichi Tanabe; Hiromi Shimamoto; Katsuyoshi Washio; Tohru Nakamura

NPN 30 GHz, 32 GHz fT complementary bipolar technology

Takahiro Onai, Eiji Ohue, Yohji Idei, Masamichi Tanabe, Hiromi Shimamoto, Katsuyoshi Washio, Tohru Nakamura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of boron diffusion layer suppressed upward diffusion of boron in the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth of both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. These results showed that the power dissipation is reduced to 1/4 in a complementary active pull-down circuit compared with an ECL circuit.

Original language	English
Title of host publication	Technical Digest - International Electron Devices Meeting
Editors	Anon
Publisher	Publ by IEEE
Pages	63-66
Number of pages	4
ISBN (Print)	0780314506
Publication status	Published - 1993
Externally published	Yes
Event	Proceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA Duration: 1993 Dec 5 → 1993 Dec 8

Publication series

Name	Technical Digest - International Electron Devices Meeting
ISSN (Print)	0163-1918

Other

Other	Proceedings of the 1993 IEEE International Electron Devices Meeting
City	Washington, DC, USA
Period	93/12/5 → 93/12/8

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

Onai, T, Ohue, E, Idei, Y, Tanabe, M, Shimamoto, H, Washio, K & Nakamura, T 1993, NPN 30 GHz, 32 GHz fT complementary bipolar technology. in Anon (ed.), Technical Digest - International Electron Devices Meeting. Technical Digest - International Electron Devices Meeting, Publ by IEEE, pp. 63-66, Proceedings of the 1993 IEEE International Electron Devices Meeting, Washington, DC, USA, 93/12/5.

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title = "NPN 30 GHz, 32 GHz fT complementary bipolar technology",

abstract = "Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of boron diffusion layer suppressed upward diffusion of boron in the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth of both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. These results showed that the power dissipation is reduced to 1/4 in a complementary active pull-down circuit compared with an ECL circuit.",

author = "Takahiro Onai and Eiji Ohue and Yohji Idei and Masamichi Tanabe and Hiromi Shimamoto and Katsuyoshi Washio and Tohru Nakamura",

year = "1993",

language = "English",

isbn = "0780314506",

series = "Technical Digest - International Electron Devices Meeting",

publisher = "Publ by IEEE",

pages = "63--66",

editor = "Anon",

booktitle = "Technical Digest - International Electron Devices Meeting",

note = "Proceedings of the 1993 IEEE International Electron Devices Meeting ; Conference date: 05-12-1993 Through 08-12-1993",

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TY - GEN

T1 - NPN 30 GHz, 32 GHz fT complementary bipolar technology

AU - Onai, Takahiro

AU - Ohue, Eiji

AU - Idei, Yohji

AU - Tanabe, Masamichi

AU - Shimamoto, Hiromi

AU - Washio, Katsuyoshi

AU - Nakamura, Tohru

PY - 1993

Y1 - 1993

N2 - Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of boron diffusion layer suppressed upward diffusion of boron in the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth of both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. These results showed that the power dissipation is reduced to 1/4 in a complementary active pull-down circuit compared with an ECL circuit.

AB - Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of boron diffusion layer suppressed upward diffusion of boron in the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth of both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. These results showed that the power dissipation is reduced to 1/4 in a complementary active pull-down circuit compared with an ECL circuit.

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M3 - Conference contribution

AN - SCOPUS:0027815085

SN - 0780314506

T3 - Technical Digest - International Electron Devices Meeting

SP - 63

EP - 66

BT - Technical Digest - International Electron Devices Meeting

A2 - Anon, null

PB - Publ by IEEE

T2 - Proceedings of the 1993 IEEE International Electron Devices Meeting

Y2 - 5 December 1993 through 8 December 1993

ER -

NPN 30 GHz, 32 GHz fT complementary bipolar technology

Abstract

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