NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)


This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

Original languageEnglish
Pages (from-to)65-68
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 2000
EventCICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA
Duration: 2000 May 212000 May 24


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