This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.
|Number of pages
|Proceedings of the Custom Integrated Circuits Conference
|Published - 2000
|CICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA
Duration: 2000 May 21 → 2000 May 24