NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors

T. Miwa, J. Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, T. Kunio

Research output: Contribution to journalArticlepeer-review

54 Citations (Scopus)


This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatiyle SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A Vdd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

Original languageEnglish
Pages (from-to)522-527
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number3
Publication statusPublished - 2001 Mar
Externally publishedYes


  • Embedded memory
  • Ferroelectric memory
  • SRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors'. Together they form a unique fingerprint.

Cite this