NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors

T. Miwa; J. Yamada; H. Koike; H. Toyoshima; K. Amanuma; S. Kobayashi; T. Tatsumi; Y. Maejima; H. Hada; T. Kunio

doi:10.1109/4.910492

NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors

T. Miwa, J. Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, T. Kunio

Research output: Contribution to journal › Article › peer-review

54 Citations (Scopus)

Abstract

This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatiyle SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V_dd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

Original language	English
Pages (from-to)	522-527
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	36
Issue number	3
DOIs	https://doi.org/10.1109/4.910492
Publication status	Published - 2001 Mar
Externally published	Yes

Keywords

Embedded memory
Ferroelectric memory
SRAM

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.910492

Cite this

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title = "NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors",

abstract = "This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatiyle SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A Vdd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.",

keywords = "Embedded memory, Ferroelectric memory, SRAM",

author = "T. Miwa and J. Yamada and H. Koike and H. Toyoshima and K. Amanuma and S. Kobayashi and T. Tatsumi and Y. Maejima and H. Hada and T. Kunio",

year = "2001",

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AU - Miwa, T.

AU - Yamada, J.

AU - Koike, H.

AU - Toyoshima, H.

AU - Amanuma, K.

AU - Kobayashi, S.

AU - Tatsumi, T.

AU - Maejima, Y.

AU - Hada, H.

AU - Kunio, T.

PY - 2001/3

Y1 - 2001/3

N2 - This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatiyle SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A Vdd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

AB - This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatiyle SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A Vdd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

KW - Embedded memory

KW - Ferroelectric memory

KW - SRAM

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NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors

Abstract

Keywords

ASJC Scopus subject areas

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