TY - GEN
T1 - On-chip checkpointing with 3D-stacked memories
AU - Sato, Masayuki
AU - Egawa, Ryusuke
AU - Takizawa, Hiroyuki
AU - Kobayashi, Hiroaki
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014
Y1 - 2014
N2 - Since deep-submicron process technologies induce soft errors, advanced computing systems face a low dependability problem. Checkpointing, which copies data required for continuing the program execution as a backup, is expected as a promising approach to keeping a high dependability. However, checkpointing causes additional memory accesses, which cause performance and energy overheads. To reduce these overheads, this paper focuses on 3D-stacking technologies. Since the technologies realize large on-chip memories with a short latency and a high bandwidth, the overheads of checkpointing are expected to decrease. In order to examine the reduction of the overheads, this paper supposes a future 3D-stacked processor-memory module, and proposes an on-chip checkpointing mechanism. The evaluation results indicate that the on-chip checkpointing with 3D-stacked memories can reduce the execution time by 15% and energy consumption by 26% on average, compared with the checkpointing mechanism with off-chip memories.
AB - Since deep-submicron process technologies induce soft errors, advanced computing systems face a low dependability problem. Checkpointing, which copies data required for continuing the program execution as a backup, is expected as a promising approach to keeping a high dependability. However, checkpointing causes additional memory accesses, which cause performance and energy overheads. To reduce these overheads, this paper focuses on 3D-stacking technologies. Since the technologies realize large on-chip memories with a short latency and a high bandwidth, the overheads of checkpointing are expected to decrease. In order to examine the reduction of the overheads, this paper supposes a future 3D-stacked processor-memory module, and proposes an on-chip checkpointing mechanism. The evaluation results indicate that the on-chip checkpointing with 3D-stacked memories can reduce the execution time by 15% and energy consumption by 26% on average, compared with the checkpointing mechanism with off-chip memories.
UR - http://www.scopus.com/inward/record.url?scp=84963826950&partnerID=8YFLogxK
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U2 - 10.1109/3DIC.2014.7152173
DO - 10.1109/3DIC.2014.7152173
M3 - Conference contribution
AN - SCOPUS:84963826950
T3 - 2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings
BT - 2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International 3D Systems Integration Conference, 3DIC 2014
Y2 - 1 December 2014 through 3 December 2014
ER -
