Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application

Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review


This paper presents an optimal design method of a multiple-valued current-mode (MVCM) integrated circuit based on dual-rail source-coupled logic, in which both power dissipation and switching delay are minimized simultaneously. The minimum delay of the MVCM circuit is determined by the optimal gate-width ratio of MOS transistors in a current mirror and a threshold detector, which are connected serially. The gate width of all of the threshold detectors is minimized while keeping the above gate-width ratio, which minimizes power dissipation. As a typical example of the MVCM logic circuit, the performance of an optimized 54 × 54-bit multiplier is estimated to be about 1.7 times faster than that of a corresponding binary device under a standard 0.5-μm CMOS process technology with a supply voltage of 1.5 V.

Original languageEnglish
Pages (from-to)40-47
Number of pages8
JournalSystems and Computers in Japan
Issue number11
Publication statusPublished - 1998 Oct


  • Current mirror
  • Differential logic circuit
  • Multiple-valued current-mode logic
  • Signed-digit multiplier
  • Source-coupled pair
  • Threshold detector


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