Optimal periodical memory allocation for logic-in-memory image processors

Masanori Hariyama; Michitaka Kameyama; Yasuhiro Kobayashi

doi:10.1109/ISVLSI.2006.69

Optimal periodical memory allocation for logic-in-memory image processors

Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design methodology for a logic-in-memory architecture where each of memory modules is connected to its dedicated processing element(PE). An efficient memory allocation to minimize the number of memory modules and PEs under a time constraint is proposed based on regularity.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages	193-198
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2006.69
Publication status	Published - 2006 Oct 9
Event	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany Duration: 2006 Mar 2 → 2006 Mar 3

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume	2006

Other

Other	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Country/Territory	Germany
City	Klarlsruhe
Period	06/3/2 → 06/3/3

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/ISVLSI.2006.69

Cite this

Hariyama, M., Kameyama, M., & Kobayashi, Y. (2006). Optimal periodical memory allocation for logic-in-memory image processors. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (pp. 193-198). [1602439] (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006). https://doi.org/10.1109/ISVLSI.2006.69

Optimal periodical memory allocation for logic-in-memory image processors. / Hariyama, Masanori; Kameyama, Michitaka; Kobayashi, Yasuhiro.
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 193-198 1602439 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hariyama, M, Kameyama, M & Kobayashi, Y 2006, Optimal periodical memory allocation for logic-in-memory image processors. in Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006., 1602439, Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, vol. 2006, pp. 193-198, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, Klarlsruhe, Germany, 06/3/2. https://doi.org/10.1109/ISVLSI.2006.69

Hariyama M, Kameyama M, Kobayashi Y. Optimal periodical memory allocation for logic-in-memory image processors. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 193-198. 1602439. (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006). doi: 10.1109/ISVLSI.2006.69

Hariyama, Masanori ; Kameyama, Michitaka ; Kobayashi, Yasuhiro. / Optimal periodical memory allocation for logic-in-memory image processors. Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. pp. 193-198 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006).

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Optimal periodical memory allocation for logic-in-memory image processors

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