Optimization of RTA process for PVD-TiN gate FinFETs

Y. X. Liu; T. Kamei; K. Endo; S. O'uchi; J. Tsukada; H. Yamauchi; Y. Ishikawa; T. Hayashida; T. Matsukawa; K. Sakamoto; A. Ogura; M. Masahara

doi:10.1109/SOI.2010.5641382

Optimization of RTA process for PVD-TiN gate FinFETs

Y. X. Liu, T. Kamei, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, T. Matsukawa, K. Sakamoto, A. Ogura, M. Masahara

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Original language	English
Title of host publication	2010 IEEE International SOI Conference, SOI 2010
DOIs	https://doi.org/10.1109/SOI.2010.5641382
Publication status	Published - 2010
Event	2010 IEEE International Silicon on Insulator Conference, SOI 2010 - San Diego, CA, United States Duration: 2010 Oct 11 → 2010 Oct 14

Publication series

Name	Proceedings - IEEE International SOI Conference
ISSN (Print)	1078-621X

Conference

Conference	2010 IEEE International Silicon on Insulator Conference, SOI 2010
Country/Territory	United States
City	San Diego, CA
Period	10/10/11 → 10/10/14

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10.1109/SOI.2010.5641382

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Liu, Y. X., Kamei, T., Endo, K., O'uchi, S., Tsukada, J., Yamauchi, H., Ishikawa, Y., Hayashida, T., Matsukawa, T., Sakamoto, K., Ogura, A., & Masahara, M. (2010). Optimization of RTA process for PVD-TiN gate FinFETs. In 2010 IEEE International SOI Conference, SOI 2010 Article 5641382 (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2010.5641382

@inproceedings{a0c1b4644d1b47e6bd3cdfa762834481,

title = "Optimization of RTA process for PVD-TiN gate FinFETs",

author = "Liu, {Y. X.} and T. Kamei and K. Endo and S. O'uchi and J. Tsukada and H. Yamauchi and Y. Ishikawa and T. Hayashida and T. Matsukawa and K. Sakamoto and A. Ogura and M. Masahara",

year = "2010",

doi = "10.1109/SOI.2010.5641382",

language = "English",

isbn = "9781424491285",

series = "Proceedings - IEEE International SOI Conference",

booktitle = "2010 IEEE International SOI Conference, SOI 2010",

note = "2010 IEEE International Silicon on Insulator Conference, SOI 2010 ; Conference date: 11-10-2010 Through 14-10-2010",

}

Liu, YX, Kamei, T, Endo, K, O'uchi, S, Tsukada, J, Yamauchi, H, Ishikawa, Y, Hayashida, T, Matsukawa, T, Sakamoto, K, Ogura, A & Masahara, M 2010, Optimization of RTA process for PVD-TiN gate FinFETs. in 2010 IEEE International SOI Conference, SOI 2010., 5641382, Proceedings - IEEE International SOI Conference, 2010 IEEE International Silicon on Insulator Conference, SOI 2010, San Diego, CA, United States, 10/10/11. https://doi.org/10.1109/SOI.2010.5641382

TY - GEN

T1 - Optimization of RTA process for PVD-TiN gate FinFETs

AU - Liu, Y. X.

AU - Kamei, T.

AU - Endo, K.

AU - O'uchi, S.

AU - Tsukada, J.

AU - Yamauchi, H.

AU - Ishikawa, Y.

AU - Hayashida, T.

AU - Matsukawa, T.

AU - Sakamoto, K.

AU - Ogura, A.

AU - Masahara, M.

PY - 2010

Y1 - 2010

UR - http://www.scopus.com/inward/record.url?scp=78650556755&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78650556755&partnerID=8YFLogxK

U2 - 10.1109/SOI.2010.5641382

DO - 10.1109/SOI.2010.5641382

M3 - Conference contribution

AN - SCOPUS:78650556755

SN - 9781424491285

T3 - Proceedings - IEEE International SOI Conference

BT - 2010 IEEE International SOI Conference, SOI 2010

T2 - 2010 IEEE International Silicon on Insulator Conference, SOI 2010

Y2 - 11 October 2010 through 14 October 2010

ER -

Optimization of RTA process for PVD-TiN gate FinFETs

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