TY - GEN
T1 - Optimizing memory layout of hyperplane ordering for vector supercomputer SX-aurora TSUBASA
AU - Watanabe, Osamu
AU - Hougi, Yuta
AU - Komatsu, Kazuhiko
AU - Sato, Masayuki
AU - Musa, Akihiro
AU - Kobayashi, Hiroaki
N1 - Funding Information:
ACKNOWLEDGMENT This research was supported in part by MEXT as “Next Generation High-Performance Computing Infrastructures and Applications R&D Program,” entitled “R&D of A Quantum-Annealing-Assisted Next Generation HPC Infrastructure and its Applications.” The authors thank Satoru Yamamoto, Takashi Furusawa, and Hironori Miyazawa of Tohoku University for their fruitful discussions and variable comments.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - This paper describes the performance optimization of hyperplane ordering methods applied to the high cost routine of the turbine simulation code called 'Numerical Turbine' for the newest vector supercomputer. The Numerical Turbine code is a computational fluid dynamics code developed at Tohoku University, which can execute large-scale parallel calculation of the entire thermal flow through multistage cascades of gas and steam turbines. The Numerical Turbine code is a memory- intensive application that requires a high memory bandwidth to achieve a high sustained performance. For this reason, it is implemented in a vector supercomputer equipped with a high-performance memory subsystem. The main performance bottleneck of the Numerical Turbine code is the time-integration routine. To vectorize the lower-upper symmetric Gauss-Seidel method used in this time integration routine, a hyperplane ordering method is used. We clarify the problems of the current hyperplane ordering methods for the newest vector supercom- puter NEC SX-Aurora TSUBASA and propose an optimized hyperplane ordering method that changes the data layout in the memory to resolve this bottleneck. Through the performance evaluation, it is clarified that the proposed hyperplane ordering can achieve further improvement of the performance by up to 2.77×, and 1.27× on average.
AB - This paper describes the performance optimization of hyperplane ordering methods applied to the high cost routine of the turbine simulation code called 'Numerical Turbine' for the newest vector supercomputer. The Numerical Turbine code is a computational fluid dynamics code developed at Tohoku University, which can execute large-scale parallel calculation of the entire thermal flow through multistage cascades of gas and steam turbines. The Numerical Turbine code is a memory- intensive application that requires a high memory bandwidth to achieve a high sustained performance. For this reason, it is implemented in a vector supercomputer equipped with a high-performance memory subsystem. The main performance bottleneck of the Numerical Turbine code is the time-integration routine. To vectorize the lower-upper symmetric Gauss-Seidel method used in this time integration routine, a hyperplane ordering method is used. We clarify the problems of the current hyperplane ordering methods for the newest vector supercom- puter NEC SX-Aurora TSUBASA and propose an optimized hyperplane ordering method that changes the data layout in the memory to resolve this bottleneck. Through the performance evaluation, it is clarified that the proposed hyperplane ordering can achieve further improvement of the performance by up to 2.77×, and 1.27× on average.
KW - Data structure
KW - Hyperplane ordering method
KW - Performance optimization
KW - Turbine simulation code
KW - Vector supercomputer
UR - http://www.scopus.com/inward/record.url?scp=85078520096&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85078520096&partnerID=8YFLogxK
U2 - 10.1109/MCHPC49590.2019.00011
DO - 10.1109/MCHPC49590.2019.00011
M3 - Conference contribution
AN - SCOPUS:85078520096
T3 - Proceedings of MCHPC 2019: Workshop on Memory Centric High Performance Computing - Held in conjunction with SC 2019: The International Conference for High Performance Computing, Networking, Storage and Analysis
SP - 25
EP - 32
BT - Proceedings of MCHPC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE/ACM Workshop on Memory Centric High Performance Computing, MCHPC 2019
Y2 - 18 November 2019
ER -