Optimum Design of n+−n− Double-Diffused Drain MOSFET to Reduce Hot-Carrier Emission

Mitsumasa Koyanagi, Hiroko Kaneko, Shinji Shimizu

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


Channel electric field reduction using an n+-n- double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep lowconcentation P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n- diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.

Original languageEnglish
Pages (from-to)562-570
Number of pages9
JournalIEEE Transactions on Electron Devices
Issue number3
Publication statusPublished - 1985 Mar
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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