Perceptron-based Cache Bypassing for Way-Adaptable Caches

Masayuki Sato; Yongcheng Chen; Haruya Kikuchi; Kazuhiko Komatsu; Hiroaki Kobayashi

doi:10.1109/CoolChips.2019.8721331

Perceptron-based Cache Bypassing for Way-Adaptable Caches

Masayuki Sato, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

A way-adaptable cache, which adaptively activates/inactivates cache ways, has the potential to reduce the cache energy consumption. However, the cache activates a non-negligible number of ways to store dead blocks, which are not reused and do not contribute to performance improvement. Therefore, this paper proposes a perceptron-based cache bypassing mechanism for the way-adaptable cache to eliminate dead blocks. The evaluation results show that the proposed mechanism can reduce the cache energy consumption by up to 67%, and 14% on average.

Original language	English
Title of host publication	IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728117485
DOIs	https://doi.org/10.1109/CoolChips.2019.8721331
Publication status	Published - 2019 May 23
Event	22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Yokohama, Japan Duration: 2019 Apr 17 → 2019 Apr 19

Publication series

Name	IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

Conference

Conference	22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019
Country/Territory	Japan
City	Yokohama
Period	19/4/17 → 19/4/19

Keywords

cache memory
energy consumption
perceptron reuse prediction
way-adaptable cache

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/CoolChips.2019.8721331

Cite this

Sato, M., Chen, Y., Kikuchi, H., Komatsu, K., & Kobayashi, H. (2019). Perceptron-based Cache Bypassing for Way-Adaptable Caches. In IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings Article 8721331 (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CoolChips.2019.8721331

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title = "Perceptron-based Cache Bypassing for Way-Adaptable Caches",

abstract = "A way-adaptable cache, which adaptively activates/inactivates cache ways, has the potential to reduce the cache energy consumption. However, the cache activates a non-negligible number of ways to store dead blocks, which are not reused and do not contribute to performance improvement. Therefore, this paper proposes a perceptron-based cache bypassing mechanism for the way-adaptable cache to eliminate dead blocks. The evaluation results show that the proposed mechanism can reduce the cache energy consumption by up to 67%, and 14% on average.",

keywords = "cache memory, energy consumption, perceptron reuse prediction, way-adaptable cache",

author = "Masayuki Sato and Yongcheng Chen and Haruya Kikuchi and Kazuhiko Komatsu and Hiroaki Kobayashi",

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year = "2019",

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doi = "10.1109/CoolChips.2019.8721331",

language = "English",

series = "IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings",

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Sato, M, Chen, Y, Kikuchi, H, Komatsu, K & Kobayashi, H 2019, Perceptron-based Cache Bypassing for Way-Adaptable Caches. in IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings., 8721331, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019, Yokohama, Japan, 19/4/17. https://doi.org/10.1109/CoolChips.2019.8721331

Perceptron-based Cache Bypassing for Way-Adaptable Caches. / Sato, Masayuki; Chen, Yongcheng; Kikuchi, Haruya et al.
IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8721331 (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Perceptron-based Cache Bypassing for Way-Adaptable Caches

AU - Sato, Masayuki

AU - Chen, Yongcheng

AU - Kikuchi, Haruya

AU - Komatsu, Kazuhiko

AU - Kobayashi, Hiroaki

PY - 2019/5/23

Y1 - 2019/5/23

N2 - A way-adaptable cache, which adaptively activates/inactivates cache ways, has the potential to reduce the cache energy consumption. However, the cache activates a non-negligible number of ways to store dead blocks, which are not reused and do not contribute to performance improvement. Therefore, this paper proposes a perceptron-based cache bypassing mechanism for the way-adaptable cache to eliminate dead blocks. The evaluation results show that the proposed mechanism can reduce the cache energy consumption by up to 67%, and 14% on average.

AB - A way-adaptable cache, which adaptively activates/inactivates cache ways, has the potential to reduce the cache energy consumption. However, the cache activates a non-negligible number of ways to store dead blocks, which are not reused and do not contribute to performance improvement. Therefore, this paper proposes a perceptron-based cache bypassing mechanism for the way-adaptable cache to eliminate dead blocks. The evaluation results show that the proposed mechanism can reduce the cache energy consumption by up to 67%, and 14% on average.

KW - cache memory

KW - energy consumption

KW - perceptron reuse prediction

KW - way-adaptable cache

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M3 - Conference contribution

AN - SCOPUS:85067126330

T3 - IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

BT - IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

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Sato M, Chen Y, Kikuchi H, Komatsu K , Kobayashi H. Perceptron-based Cache Bypassing for Way-Adaptable Caches. In IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8721331. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings). doi: 10.1109/CoolChips.2019.8721331

Perceptron-based Cache Bypassing for Way-Adaptable Caches

Abstract

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Keywords

UN SDGs

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