TY - GEN
T1 - Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem
AU - Mondigo, Antoniette
AU - Sano, Kentaro
AU - Takizawa, Hirovuki
N1 - Funding Information:
This research was partially supported by Grant-in-Aid for Scientific Research (B) No.17H01706 from MEXT, Japan. The authors thank the support of Intel university program.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/8/23
Y1 - 2018/8/23
N2 - To precisely evaluate the sustained performance and scalability of pipelined multiple FPGAs, this paper presents the implementation of a high-speed communication subsystem for a deeply pipelined stream computing platform. Internally, a pipeline of hardware modules for a domain-specific application is implemented in the FPGAs, where they are directly connected through their serial transceiver links. The necessary inter-FPGA communication subsystem with a flow control mechanism is implemented with Intel Arria 10 FPGAs, where the resource consumption and sustained network throughput are obtained, which averages at 7.92 GB/s. Performance estimation of a fluid simulation using the measured inter-FPGA network parameters is shown for a varied pipeline depth with explored temporal and spatial parallel options. Results show that the proposed platform with 16 FPGAs is estimated to achieve a sustained performance of 4.8 TFlops and may be scaled further by deepening the pipeline with even up to 128 FPGAs.
AB - To precisely evaluate the sustained performance and scalability of pipelined multiple FPGAs, this paper presents the implementation of a high-speed communication subsystem for a deeply pipelined stream computing platform. Internally, a pipeline of hardware modules for a domain-specific application is implemented in the FPGAs, where they are directly connected through their serial transceiver links. The necessary inter-FPGA communication subsystem with a flow control mechanism is implemented with Intel Arria 10 FPGAs, where the resource consumption and sustained network throughput are obtained, which averages at 7.92 GB/s. Performance estimation of a fluid simulation using the measured inter-FPGA network parameters is shown for a varied pipeline depth with explored temporal and spatial parallel options. Results show that the proposed platform with 16 FPGAs is estimated to achieve a sustained performance of 4.8 TFlops and may be scaled further by deepening the pipeline with even up to 128 FPGAs.
KW - communication
KW - deep pipeline
KW - flow control
KW - multiple FPGAs
KW - performance estimation
KW - stream computing
UR - http://www.scopus.com/inward/record.url?scp=85053477662&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85053477662&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2018.8445100
DO - 10.1109/ASAP.2018.8445100
M3 - Conference contribution
AN - SCOPUS:85053477662
SN - 9781538674796
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
BT - 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018
Y2 - 10 July 2018 through 12 July 2018
ER -