Performance evaluation of a multivalued rsa encryption vlsi

This paper discusses performance evaluation of a multiple‐valued RSA encryption VLSI based on radix‐4 signed‐digit (SD) number arithmetic that is very useful for long word length arithmetic. In the arithmetic unit of the encryption VLSI, a signed‐digit adder (SD adder) is used, which is constructed with bidirectional current‐mode circuits. Also, the input/output interface circuit of the radix‐4 adder is considered for construction of a high‐speed SD full adder. A layout of the encryption VLSI including this multiple‐valued SD full adder is designed by the 2‐m̈m CMOS rule and the chip size is 9.1 7.4 mm² for 512‐bit word length encryption. By performance evaluation with extracting SPICE parameters from the layout, an encryption rate of 85 bit/s can be obtained which is a factor of eight times faster than that of the corresponding binary one.