Performance evaluation of NEC SX-9 using real science and engineering applications

Takashi Soga, Akihiro Musa, Youichi Shimomura, Ryusuke Egawa, Ken'Ichi Itakura, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

32 Citations (Scopus)

Abstract

This paper describes a new-generation vector parallel supercomputer, NEC SX-9 system. The SX-9 processor has an outstanding core to achieve over 100Gflop/s, and a software-controllable on-chip cache to keep the high ratio of the memory bandwidth to the floating-point operation rate. Moreover, its large SMP nodes of 16 vector processors with 1.6Tflop/s performance and 1TB memory are connected with dedicated network switches, which can achieve inter-node communication at 128GB/s per direction. The sustained performance of the SX-9 processor is evaluated using six practical applications in comparison with conventional vector processors and the latest scalar processor such as Nehalem-EP. Based on the results, this paper discusses the performance tuning strategies for new-generation vector systems. An SX-9 system of 16 nodes is also evaluated by using the HPC challenge benchmark suite and a CFD code. Those evaluation results clarify the highest sustained performance and scalability of the SX-9 system.

Original languageEnglish
Title of host publicationProceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09
DOIs
Publication statusPublished - 2009
EventConference on High Performance Computing Networking, Storage and Analysis, SC '09 - Portland, OR, United States
Duration: 2009 Nov 142009 Nov 20

Publication series

NameProceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09

Conference

ConferenceConference on High Performance Computing Networking, Storage and Analysis, SC '09
Country/TerritoryUnited States
CityPortland, OR
Period09/11/1409/11/20

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