Phase-mode pipelined parallel multiplier

Takeshi Onomi; Kiyoshi Yanagisawa; Masashi Seki; Koji Nakajima

doi:10.1109/77.919402

Phase-mode pipelined parallel multiplier

Takeshi Onomi, Kiyoshi Yanagisawa, Masashi Seki, Koji Nakajima

Research output: Contribution to journal › Conference article › peer-review

9 Citations (Scopus)

Abstract

We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5kA/cm² Nb/AlOx/Nb junctions can operate over 10 CHz.

Original language	English
Pages (from-to)	541-544
Number of pages	4
Journal	IEEE Transactions on Applied Superconductivity
Volume	11
Issue number	1 I
DOIs	https://doi.org/10.1109/77.919402
Publication status	Published - 2001 Mar
Externally published	Yes
Event	2000 Applied Superconductivity Conference - Virginia Beach, VA, United States Duration: 2000 Sept 17 → 2000 Sept 22

Keywords

Multiplier
Phase mode
Pipeline
Single flux quantum

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/77.919402

Cite this

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title = "Phase-mode pipelined parallel multiplier",

abstract = "We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5kA/cm2 Nb/AlOx/Nb junctions can operate over 10 CHz.",

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author = "Takeshi Onomi and Kiyoshi Yanagisawa and Masashi Seki and Koji Nakajima",

note = "Funding Information: Manuscript received Sept. 18,2000. This work was supported in part by Special Coordination Funds for promoting Science and Technology of the Science and Technology Agency of the Japanese Government.; 2000 Applied Superconductivity Conference ; Conference date: 17-09-2000 Through 22-09-2000",

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T1 - Phase-mode pipelined parallel multiplier

AU - Onomi, Takeshi

AU - Yanagisawa, Kiyoshi

AU - Seki, Masashi

AU - Nakajima, Koji

N1 - Funding Information: Manuscript received Sept. 18,2000. This work was supported in part by Special Coordination Funds for promoting Science and Technology of the Science and Technology Agency of the Japanese Government.

PY - 2001/3

Y1 - 2001/3

N2 - We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5kA/cm2 Nb/AlOx/Nb junctions can operate over 10 CHz.

AB - We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5kA/cm2 Nb/AlOx/Nb junctions can operate over 10 CHz.

KW - Multiplier

KW - Phase mode

KW - Pipeline

KW - Single flux quantum

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JO - IEEE Transactions on Applied Superconductivity

JF - IEEE Transactions on Applied Superconductivity

IS - 1 I

T2 - 2000 Applied Superconductivity Conference

Y2 - 17 September 2000 through 22 September 2000

ER -

Phase-mode pipelined parallel multiplier

Abstract

Keywords

ASJC Scopus subject areas

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