Phase-mode pipelined parallel multiplier

Takeshi Onomi, Kiyoshi Yanagisawa, Masashi Seki, Koji Nakajima

Research output: Contribution to journalConference articlepeer-review

9 Citations (Scopus)


We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5kA/cm2 Nb/AlOx/Nb junctions can operate over 10 CHz.

Original languageEnglish
Pages (from-to)541-544
Number of pages4
JournalIEEE Transactions on Applied Superconductivity
Issue number1 I
Publication statusPublished - 2001 Mar
Externally publishedYes
Event2000 Applied Superconductivity Conference - Virginia Beach, VA, United States
Duration: 2000 Sept 172000 Sept 22


  • Multiplier
  • Phase mode
  • Pipeline
  • Single flux quantum

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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