PMAC++:incrementalmac scheme adaptableto lightweight block ciphers

Maya Oda, Rei Veno, Akiko Inoue, Kazuhiko Minematsu, Naofumi Homma

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.

Original languageEnglish
Title of host publication2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728133201
Publication statusPublished - 2020
Event52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
Duration: 2020 Oct 102020 Oct 21

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310


Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
CityVirtual, Online


  • Crypto graphic hard ware architecture
  • Light weight blockciphers
  • Memory security
  • Message authentication code


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