This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.