PMAC++:incrementalmac scheme adaptableto lightweight block ciphers

Maya Oda; Rei Veno; Akiko Inoue; Kazuhiko Minematsu; Naofumi Homma

PMAC++:incrementalmac scheme adaptableto lightweight block ciphers

Maya Oda, Rei Veno, Akiko Inoue, Kazuhiko Minematsu, Naofumi Homma

RIEC - Information Communication Platforms Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.

Original language	English
Title of host publication	2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728133201
Publication status	Published - 2020
Event	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 2020 Oct 10 → 2020 Oct 21

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2020-October
ISSN (Print)	0271-4310

Conference

Conference	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
City	Virtual, Online
Period	20/10/10 → 20/10/21

Keywords

Crypto graphic hard ware architecture
Light weight blockciphers
Memory security
Message authentication code

Cite this

Oda, M., Veno, R., Inoue, A., Minematsu, K., & Homma, N. (2020). PMAC++:incrementalmac scheme adaptableto lightweight block ciphers. In 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings Article 9180779 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October). Institute of Electrical and Electronics Engineers Inc..

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title = "PMAC++:incrementalmac scheme adaptableto lightweight block ciphers",

abstract = "This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.",

keywords = "Crypto graphic hard ware architecture, Light weight blockciphers, Memory security, Message authentication code",

author = "Maya Oda and Rei Veno and Akiko Inoue and Kazuhiko Minematsu and Naofumi Homma",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

year = "2020",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",

address = "United States",

}

Oda, M, Veno, R, Inoue, A, Minematsu, K & Homma, N 2020, PMAC++:incrementalmac scheme adaptableto lightweight block ciphers. in 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings., 9180779, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2020-October, Institute of Electrical and Electronics Engineers Inc., 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, Virtual, Online, 20/10/10.

PMAC++:incrementalmac scheme adaptableto lightweight block ciphers. / Oda, Maya; Veno, Rei; Inoue, Akiko et al.
2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9180779 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - PMAC++:incrementalmac scheme adaptableto lightweight block ciphers

AU - Oda, Maya

AU - Veno, Rei

AU - Inoue, Akiko

AU - Minematsu, Kazuhiko

AU - Homma, Naofumi

PY - 2020

Y1 - 2020

N2 - This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.

AB - This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.

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KW - Light weight blockciphers

KW - Memory security

KW - Message authentication code

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M3 - Conference contribution

AN - SCOPUS:85109297294

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -

PMAC++:incrementalmac scheme adaptableto lightweight block ciphers

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