Process Integration for FlexTrate                         TM

Tak Fukushima; Yuki Susumago; Hisashi Kino; Tetsu Tanaka; Arsalan Alam; Amir Hanna; Subramanian S. Iyer

doi:10.1109/IFETC.2018.8584029

Process Integration for FlexTrate ^TM

Tak Fukushima, Yuki Susumago, Hisashi Kino, Tetsu Tanaka, Arsalan Alam, Amir Hanna, Subramanian S. Iyer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

We fabricate FlexTrate ^TM that is highly integrated bendable and/or rollable electronic systems in which various Si and/or III-V chips are embedded in elastomers and interconnected at the wafer level. This paper describes the process integration of the FlexTrate ^TM using massively parallel capillary self-assembly and a new single stress buffer layer technologies to form fine-pitch interconnection between the embedded neighboring chips and characterize the electrical/mechanical properties.

Original language	English
Title of host publication	2018 International Flexible Electronics Technology Conference, IFETC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538633571
DOIs	https://doi.org/10.1109/IFETC.2018.8584029
Publication status	Published - 2018 Dec 19
Event	2018 International Flexible Electronics Technology Conference, IFETC 2018 - Ottawa, Canada Duration: 2018 Aug 7 → 2018 Aug 9

Publication series

Name	2018 International Flexible Electronics Technology Conference, IFETC 2018

Conference

Conference	2018 International Flexible Electronics Technology Conference, IFETC 2018
Country/Territory	Canada
City	Ottawa
Period	18/8/7 → 18/8/9

Keywords

FOWLP
Flexible hybrid electronics
Self-assembly

Access to Document

10.1109/IFETC.2018.8584029

Cite this

Fukushima, T., Susumago, Y., Kino, H., Tanaka, T., Alam, A., Hanna, A., & Iyer, S. S. (2018). Process Integration for FlexTrate ^TM In 2018 International Flexible Electronics Technology Conference, IFETC 2018 Article 8584029 (2018 International Flexible Electronics Technology Conference, IFETC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IFETC.2018.8584029

Fukushima, Tak ; Susumago, Yuki ; Kino, Hisashi et al. / Process Integration for FlexTrate ^TM 2018 International Flexible Electronics Technology Conference, IFETC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. (2018 International Flexible Electronics Technology Conference, IFETC 2018).

@inproceedings{7df020569c964e629ca22b11f897657c,

title = " Process Integration for FlexTrate TM ",

abstract = " We fabricate FlexTrate TM that is highly integrated bendable and/or rollable electronic systems in which various Si and/or III-V chips are embedded in elastomers and interconnected at the wafer level. This paper describes the process integration of the FlexTrate TM using massively parallel capillary self-assembly and a new single stress buffer layer technologies to form fine-pitch interconnection between the embedded neighboring chips and characterize the electrical/mechanical properties.",

keywords = "FOWLP, Flexible hybrid electronics, Self-assembly",

author = "Tak Fukushima and Yuki Susumago and Hisashi Kino and Tetsu Tanaka and Arsalan Alam and Amir Hanna and Iyer, {Subramanian S.}",

note = "Funding Information: ACKNOWLEDGMENT The Defense Advanced Research Projects Agency (DARPA) through ONR grant N00014-16-1-263 and NBMC supported this work. This material is also based on research sponsored by Air Force Research Laboratory under agreement number FA8650-13-2-7311. Funding Information: This work was supported by the Defense Advanced Research Projects Agency (DARPA) through ONR grant 00014-16-1-263, NBMC, and Air Force Research Laboratory under agreement number FA8650-13-2-7311. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Flexible Electronics Technology Conference, IFETC 2018 ; Conference date: 07-08-2018 Through 09-08-2018",

year = "2018",

month = dec,

day = "19",

doi = "10.1109/IFETC.2018.8584029",

language = "English",

series = "2018 International Flexible Electronics Technology Conference, IFETC 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2018 International Flexible Electronics Technology Conference, IFETC 2018",

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Fukushima, T, Susumago, Y, Kino, H , Tanaka, T, Alam, A, Hanna, A & Iyer, SS 2018, Process Integration for FlexTrate ^TM in 2018 International Flexible Electronics Technology Conference, IFETC 2018., 8584029, 2018 International Flexible Electronics Technology Conference, IFETC 2018, Institute of Electrical and Electronics Engineers Inc., 2018 International Flexible Electronics Technology Conference, IFETC 2018, Ottawa, Canada, 18/8/7. https://doi.org/10.1109/IFETC.2018.8584029

Process Integration for FlexTrate ^TM . / Fukushima, Tak; Susumago, Yuki; Kino, Hisashi et al.
2018 International Flexible Electronics Technology Conference, IFETC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 8584029 (2018 International Flexible Electronics Technology Conference, IFETC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kino, Hisashi

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AU - Alam, Arsalan

AU - Hanna, Amir

AU - Iyer, Subramanian S.

N1 - Funding Information: ACKNOWLEDGMENT The Defense Advanced Research Projects Agency (DARPA) through ONR grant N00014-16-1-263 and NBMC supported this work. This material is also based on research sponsored by Air Force Research Laboratory under agreement number FA8650-13-2-7311. Funding Information: This work was supported by the Defense Advanced Research Projects Agency (DARPA) through ONR grant 00014-16-1-263, NBMC, and Air Force Research Laboratory under agreement number FA8650-13-2-7311. Publisher Copyright: © 2018 IEEE.

PY - 2018/12/19

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N2 - We fabricate FlexTrate TM that is highly integrated bendable and/or rollable electronic systems in which various Si and/or III-V chips are embedded in elastomers and interconnected at the wafer level. This paper describes the process integration of the FlexTrate TM using massively parallel capillary self-assembly and a new single stress buffer layer technologies to form fine-pitch interconnection between the embedded neighboring chips and characterize the electrical/mechanical properties.

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Fukushima T, Susumago Y, Kino H , Tanaka T, Alam A, Hanna A et al. Process Integration for FlexTrate ^TM In 2018 International Flexible Electronics Technology Conference, IFETC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. 8584029. (2018 International Flexible Electronics Technology Conference, IFETC 2018). doi: 10.1109/IFETC.2018.8584029