TY - GEN
T1 - Process-variation-resilient OTA using MTJ-based multi-level resistance control
AU - Natsui, Masanori
AU - Nagashima, Takaaki
AU - Hanyu, Takahiro
PY - 2012
Y1 - 2012
N2 - A process, voltage, and temperature (PVT) variation conditioning technique using magnetic tunnel junction (MTJ) devices, whose resistance values are programmable, is proposed for realizing a wider design margin in analog integrated circuits. Because MTJ devices are fabricated on top of the CMOS integrated circuit layer, there is a small chip-area overhead for inserting additional MTJ devices into analog circuits, which makes it easy to use the variation-conditioning technique frequently on the entire chip. Additionally, the use of series-parallel connections for MTJ devices allows more flexible adjustment of the resistance. As a typical example, we demonstrate that under 0.18 mm CMOS technology, a simple operational Tran conductance amplifier (OTA) using the proposed technique outperforms a conventional OTA without any variation-conditioning technique.
AB - A process, voltage, and temperature (PVT) variation conditioning technique using magnetic tunnel junction (MTJ) devices, whose resistance values are programmable, is proposed for realizing a wider design margin in analog integrated circuits. Because MTJ devices are fabricated on top of the CMOS integrated circuit layer, there is a small chip-area overhead for inserting additional MTJ devices into analog circuits, which makes it easy to use the variation-conditioning technique frequently on the entire chip. Additionally, the use of series-parallel connections for MTJ devices allows more flexible adjustment of the resistance. As a typical example, we demonstrate that under 0.18 mm CMOS technology, a simple operational Tran conductance amplifier (OTA) using the proposed technique outperforms a conventional OTA without any variation-conditioning technique.
KW - Circuit conditioning
KW - Magnetic tunnel junction device
KW - Operational conductance amplifier
KW - PVT variation
UR - http://www.scopus.com/inward/record.url?scp=84864205698&partnerID=8YFLogxK
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U2 - 10.1109/ISMVL.2012.52
DO - 10.1109/ISMVL.2012.52
M3 - Conference contribution
AN - SCOPUS:84864205698
SN - 9780769546735
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 214
EP - 219
BT - Proceedings - IEEE 42nd International Symposium on Multiple-Valued Logic, ISMVL 2012
T2 - 42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012
Y2 - 14 May 2012 through 16 May 2012
ER -