Processor SER Estimation with ACE Bit Analysis

Ting Shuo Hsu; Dun An Yang; Wang Liao; Masatoshi Itoh; Masanori Hashimoto; Jing Jia Liou

doi:10.1109/RADECS53308.2021.9954474

Processor SER Estimation with ACE Bit Analysis

Ting Shuo Hsu, Dun An Yang, Wang Liao, Masatoshi Itoh, Masanori Hashimoto, Jing Jia Liou

Cyclotron and Radioisotope Center (CYRIC)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Estimating the soft error rate (SER) for processors is imperative to adopt a proper hardening technique for increasing the system reliability. Aiming to estimate the functional error rates, we propose to scale the baseline SER estimated with physical memory sizes by the fraction of architecturally correct execution (ACE) bits of memory elements (SRAM, caches and registers). We compared the scaled SER with the measured SER under neutron irradiation for a multi-core processor and confirmed a good consistency.

Original language	English
Title of host publication	RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665437943
DOIs	https://doi.org/10.1109/RADECS53308.2021.9954474
Publication status	Published - 2021
Event	21st European Conference on Radiation and its Effects on Components and Systems, RADECS 2021 - Vienna, Austria Duration: 2021 Sept 13 → 2021 Sept 17

Publication series

Name	RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems

Conference

Conference	21st European Conference on Radiation and its Effects on Components and Systems, RADECS 2021
Country/Territory	Austria
City	Vienna
Period	21/9/13 → 21/9/17

Keywords

ACE
Irradiation Test
Processor
RISC-V
SER

ASJC Scopus subject areas

Space and Planetary Science
Instrumentation
Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials
Radiation

Access to Document

10.1109/RADECS53308.2021.9954474

Cite this

Hsu, T. S., Yang, D. A., Liao, W., Itoh, M., Hashimoto, M., & Liou, J. J. (2021). Processor SER Estimation with ACE Bit Analysis. In RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems (RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RADECS53308.2021.9954474

Processor SER Estimation with ACE Bit Analysis. / Hsu, Ting Shuo; Yang, Dun An; Liao, Wang et al.

RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems. Institute of Electrical and Electronics Engineers Inc., 2021. (RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hsu, TS, Yang, DA, Liao, W, Itoh, M, Hashimoto, M & Liou, JJ 2021, Processor SER Estimation with ACE Bit Analysis. in RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems. RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems, Institute of Electrical and Electronics Engineers Inc., 21st European Conference on Radiation and its Effects on Components and Systems, RADECS 2021, Vienna, Austria, 21/9/13. https://doi.org/10.1109/RADECS53308.2021.9954474

Hsu TS, Yang DA, Liao W, Itoh M, Hashimoto M, Liou JJ. Processor SER Estimation with ACE Bit Analysis. In RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems. Institute of Electrical and Electronics Engineers Inc. 2021. (RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems). doi: 10.1109/RADECS53308.2021.9954474

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title = "Processor SER Estimation with ACE Bit Analysis",

abstract = "Estimating the soft error rate (SER) for processors is imperative to adopt a proper hardening technique for increasing the system reliability. Aiming to estimate the functional error rates, we propose to scale the baseline SER estimated with physical memory sizes by the fraction of architecturally correct execution (ACE) bits of memory elements (SRAM, caches and registers). We compared the scaled SER with the measured SER under neutron irradiation for a multi-core processor and confirmed a good consistency.",

keywords = "ACE, Irradiation Test, Processor, RISC-V, SER",

author = "Hsu, {Ting Shuo} and Yang, {Dun An} and Wang Liao and Masatoshi Itoh and Masanori Hashimoto and Liou, {Jing Jia}",

note = "Funding Information: This work is supported by JST-OPERA Program Grant Number JPMJOP1721 and Grant-in-Aid for Scientific Research (S) from JSPS under Grant JP19H05664. Publisher Copyright: {\textcopyright} 2021 IEEE.; 21st European Conference on Radiation and its Effects on Components and Systems, RADECS 2021 ; Conference date: 13-09-2021 Through 17-09-2021",

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doi = "10.1109/RADECS53308.2021.9954474",

language = "English",

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AU - Hsu, Ting Shuo

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AU - Itoh, Masatoshi

AU - Hashimoto, Masanori

AU - Liou, Jing Jia

N1 - Funding Information: This work is supported by JST-OPERA Program Grant Number JPMJOP1721 and Grant-in-Aid for Scientific Research (S) from JSPS under Grant JP19H05664. Publisher Copyright: © 2021 IEEE.

PY - 2021

Y1 - 2021

N2 - Estimating the soft error rate (SER) for processors is imperative to adopt a proper hardening technique for increasing the system reliability. Aiming to estimate the functional error rates, we propose to scale the baseline SER estimated with physical memory sizes by the fraction of architecturally correct execution (ACE) bits of memory elements (SRAM, caches and registers). We compared the scaled SER with the measured SER under neutron irradiation for a multi-core processor and confirmed a good consistency.

AB - Estimating the soft error rate (SER) for processors is imperative to adopt a proper hardening technique for increasing the system reliability. Aiming to estimate the functional error rates, we propose to scale the baseline SER estimated with physical memory sizes by the fraction of architecturally correct execution (ACE) bits of memory elements (SRAM, caches and registers). We compared the scaled SER with the measured SER under neutron irradiation for a multi-core processor and confirmed a good consistency.

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KW - Irradiation Test

KW - Processor

KW - RISC-V

KW - SER

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BT - RADECS 2021 - European Conference on Radiation and its Effects on Components and Systems

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ER -

Processor SER Estimation with ACE Bit Analysis

Abstract

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Conference

Keywords

ASJC Scopus subject areas

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