TY - JOUR
T1 - Proposal of a multi-layer channel MOSFET
T2 - The application of selective etching for Si/SiGe stacked layers
AU - Sasaki, D.
AU - Ohmi, S.
AU - Sakuraba, M.
AU - Murota, J.
AU - Sakai, T.
N1 - Funding Information:
This work was partially supported by a Grant-in-Aid for Scientific Research (B) (No. 13450138) from the Ministry of Education, Culture, Sports, Science, and Technology.
PY - 2004/3/15
Y1 - 2004/3/15
N2 - A multi-layer channel MOSFET (ML-MOSFET) and its fabrication process were proposed for future CMOS application. ML-MOSFET has multi-Si channel layers stacked vertically, so that the drain current per 1 μm gate width on wafer is expected to increase with the number of channel layers compared to conventional double-gate MOSFET. I on = 3.9 mA/μm was obtained for ML-MOSFET with three Si channel layers (L g : 10 nm, T Si : 2.5 nm) by the device simulation. Fabrication process of multi-layer channel using selective etching for SiGe/Si stacked layers was also investigated.
AB - A multi-layer channel MOSFET (ML-MOSFET) and its fabrication process were proposed for future CMOS application. ML-MOSFET has multi-Si channel layers stacked vertically, so that the drain current per 1 μm gate width on wafer is expected to increase with the number of channel layers compared to conventional double-gate MOSFET. I on = 3.9 mA/μm was obtained for ML-MOSFET with three Si channel layers (L g : 10 nm, T Si : 2.5 nm) by the device simulation. Fabrication process of multi-layer channel using selective etching for SiGe/Si stacked layers was also investigated.
KW - Current drivability
KW - Double gate
KW - MOSFET
KW - Multi-layer channel
KW - SiGe selective etching
KW - Three-dimensional structure
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U2 - 10.1016/j.apsusc.2003.08.107
DO - 10.1016/j.apsusc.2003.08.107
M3 - Article
AN - SCOPUS:1142280309
SN - 0169-4332
VL - 224
SP - 270
EP - 273
JO - Applied Surface Science
JF - Applied Surface Science
IS - 1-4
ER -