Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors

Rihito Kuroda, Akinobu Teramoto, Shigetoshi Sugawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

Using the developed array test circuit, both static and temporal electrical characteristics of over million transistors/shot were measured with the accuracy of 60 μVrms to analyze and reduce random telegraph noise (RTN) toward high S/N CMOS image sensors. Statistical evaluation results of RTN parameters such as time constants and amplitude and their behaviors toward transistor device structures and operation conditions are summarized. Application to high S/N CMOS image sensor is also described.

Original languageEnglish
Title of host publication2016 29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages46-51
Number of pages6
ISBN (Electronic)9781467387934
DOIs
Publication statusPublished - 2016 May 20
Event29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Yokohama, Japan
Duration: 2016 Mar 282016 Mar 31

Publication series

NameIEEE International Conference on Microelectronic Test Structures
Volume2016-May

Other

Other29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016
Country/TerritoryJapan
CityYokohama
Period16/3/2816/3/31

Keywords

  • CMOS image sensor
  • arrayed test circuit
  • random telegraph noise

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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