TY - GEN
T1 - Ray tracing hardware system using plane-sphere intersections
AU - Kaeriyama, Yoshiyuki
AU - Zaitsu, Daichi
AU - Komatsu, Kazuhiko
AU - Suzuki, Kenichi
AU - Nakamura, Tadao
AU - Ohba, Nobuyuki
PY - 2006
Y1 - 2006
N2 - Ray tracing is a global illumination based rendering method widely used in computer graphics. Although it generates photo-realistic images, it requires a large number of computations. In ray tracing, the ray-object intersection test is one of the dominant factors for the processing speed. To accelerate the intersection test, we propose a new method based on a plane-sphere intersection algorithm, and show a hardware system using an FPGA. The computations used in the method are highly pipelined and parallelized by optimizing the balance between the computation speed and the memory data bandwidth. As a result, the prototype makes full use of 512 DSP cores built in Xilinx Vertex-4 SX FPGA, and the average utilization of the DSP cores is close to 90%. The simulation results show that the proposed system running at 160MHz performs the intersection test a few hundred times faster than a commodity PC with a 3.4GHz Pentium 4.
AB - Ray tracing is a global illumination based rendering method widely used in computer graphics. Although it generates photo-realistic images, it requires a large number of computations. In ray tracing, the ray-object intersection test is one of the dominant factors for the processing speed. To accelerate the intersection test, we propose a new method based on a plane-sphere intersection algorithm, and show a hardware system using an FPGA. The computations used in the method are highly pipelined and parallelized by optimizing the balance between the computation speed and the memory data bandwidth. As a result, the prototype makes full use of 512 DSP cores built in Xilinx Vertex-4 SX FPGA, and the average utilization of the DSP cores is close to 90%. The simulation results show that the proposed system running at 160MHz performs the intersection test a few hundred times faster than a commodity PC with a 3.4GHz Pentium 4.
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U2 - 10.1109/FPL.2006.311231
DO - 10.1109/FPL.2006.311231
M3 - Conference contribution
AN - SCOPUS:46249083869
SN - 142440312X
SN - 9781424403127
T3 - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
SP - 315
EP - 320
BT - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
T2 - 2006 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 28 August 2006 through 30 August 2006
ER -