Reconfigurable synchronized dataflow processor

Hiroshi Sasaki; Hitoshi Maruyama; Hideaki Tsukioka; Nobuyoshi Shoji; Hiroaki Kobayashi; Tadao Nakamura

doi:10.1145/368434.368490

Reconfigurable synchronized dataflow processor

Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.

Original language	English
Title of host publication	Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Pages	27-28
Number of pages	2
DOIs	https://doi.org/10.1145/368434.368490
Publication status	Published - 2000
Event	2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama, Japan Duration: 2000 Jan 25 → 2000 Jan 28

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Country/Territory	Japan
City	Yokohama
Period	00/1/25 → 00/1/28

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10.1145/368434.368490

Cite this

@inproceedings{6255aefeda144b808bb3903690805c55,

title = "Reconfigurable synchronized dataflow processor",

abstract = "This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.",

author = "Hiroshi Sasaki and Hitoshi Maruyama and Hideaki Tsukioka and Nobuyoshi Shoji and Hiroaki Kobayashi and Tadao Nakamura",

year = "2000",

doi = "10.1145/368434.368490",

language = "English",

isbn = "0780359747",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "27--28",

booktitle = "Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000",

note = "2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 ; Conference date: 25-01-2000 Through 28-01-2000",

}

Sasaki, H, Maruyama, H, Tsukioka, H, Shoji, N, Kobayashi, H & Nakamura, T 2000, Reconfigurable synchronized dataflow processor. in Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 27-28, 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000, Yokohama, Japan, 00/1/25. https://doi.org/10.1145/368434.368490

Reconfigurable synchronized dataflow processor. / Sasaki, Hiroshi; Maruyama, Hitoshi; Tsukioka, Hideaki et al.
Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. 2000. p. 27-28 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Reconfigurable synchronized dataflow processor

AU - Sasaki, Hiroshi

AU - Maruyama, Hitoshi

AU - Tsukioka, Hideaki

AU - Shoji, Nobuyoshi

AU - Kobayashi, Hiroaki

AU - Nakamura, Tadao

PY - 2000

Y1 - 2000

N2 - This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.

AB - This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.

UR - http://www.scopus.com/inward/record.url?scp=84884681398&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84884681398&partnerID=8YFLogxK

U2 - 10.1145/368434.368490

DO - 10.1145/368434.368490

M3 - Conference contribution

AN - SCOPUS:84884681398

SN - 0780359747

SN - 9780780359741

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 27

EP - 28

BT - Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000

T2 - 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000

Y2 - 25 January 2000 through 28 January 2000

ER -

Reconfigurable synchronized dataflow processor

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