TY - JOUR
T1 - Reductant-assisted self-assembly with cu/sn microbump for three-dimensional heterogeneous integration
AU - Ito, Yuka
AU - Fukushima, Takafumi
AU - Lee, Kang Wook
AU - Choki, Koji
AU - Tanaka, Tetsu
AU - Koyanagi, Mitsumasa
PY - 2013/4
Y1 - 2013/4
N2 - To establish liquid-assisted assembly processes applicable to heterogeneous system integrations, we present flip-chip self-assembly of dies with Cu/Sn microbumps using the difference in droplet wetting between hydrophilic and hydrophobic areas. Flip-chip self-assembly is assisted by a water-soluble flux that has high surface tension comparable to that of pure water and contains an additive of a reducing agent for metal oxides. Control of the additive concentration in the flux provides high wettability contrast that enable spontaneous and precise alignment of chips to hydrophilic areas formed on substrates within 5 m in alignment accuracy. In the subsequent chip bonding process, the reductant can eliminate the metal oxide layer and improve the solder wettability of Sn to the corresponding electrode pads formed on the chips. In addition, we confirm, through electrical characteristic evaluation after thermal compression bonding, that the resulting daisy chain formed between the substrates and self-assembled chips with the flux shows sufficiently low contact resistance of below 20m/bump without disconnection.
AB - To establish liquid-assisted assembly processes applicable to heterogeneous system integrations, we present flip-chip self-assembly of dies with Cu/Sn microbumps using the difference in droplet wetting between hydrophilic and hydrophobic areas. Flip-chip self-assembly is assisted by a water-soluble flux that has high surface tension comparable to that of pure water and contains an additive of a reducing agent for metal oxides. Control of the additive concentration in the flux provides high wettability contrast that enable spontaneous and precise alignment of chips to hydrophilic areas formed on substrates within 5 m in alignment accuracy. In the subsequent chip bonding process, the reductant can eliminate the metal oxide layer and improve the solder wettability of Sn to the corresponding electrode pads formed on the chips. In addition, we confirm, through electrical characteristic evaluation after thermal compression bonding, that the resulting daisy chain formed between the substrates and self-assembled chips with the flux shows sufficiently low contact resistance of below 20m/bump without disconnection.
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U2 - 10.7567/JJAP.52.04CB09
DO - 10.7567/JJAP.52.04CB09
M3 - Article
AN - SCOPUS:84880816961
SN - 0021-4922
VL - 52
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 4 PART 2
M1 - 04CB09
ER -