Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations

This paper introduces redundant spin-transfer-torque (STT) magnetic tunnel junction (MTJ) based nonvolatile flip-flops (NVFFs) for low write-error rate (WER) operations. STT-MTJ NVFFs are key components for ultra-low power VLSI systems thanks to zero standby current, but suffers from write errors due to probabilistic switching, causing a failure backup/restore operation. To reduce the WER, redundant STT-MTJ devices are exploited in the proposed NVFFs. As one-bit information is redundantly represented, it is correctly stored upon a few bit write errors, lowering WERs compared to a conventional NVFF at the same write time. Three different redundant structures are presented and discussed in terms of WER and write energy dissipation. For performance comparisons, the proposed redundant STT-MTJ NVFFs are designed using hybrid 90nm CMOS and MTJ technologies and evaluated using NSSPICE that handles both transistors and MTJs. The simulation results show that the proposed NVFF reduces the write time to 36.2% and the write energy to 70.7% at a WER of 10^-12 compared to the conventional NVFF.