Room temperature bonding of InGaAs wafers using thin Ge films

M. Uomoto; Y. Yamada; T. Hoshi; M. Nada; T. Shimatsu

doi:10.23919/LTB-3D.2017.7947446

Room temperature bonding of InGaAs wafers using thin Ge films

M. Uomoto, Y. Yamada, T. Hoshi, M. Nada, T. Shimatsu

Advanced Interdisciplinary Research Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Room temperature bonding of InGaAs wafers using thin Ge films was studied. Wafers were bonded even with 0.5 nm thick Ge film on each side. Bonded wafers showed strong bonding force after annealing at 340 ^oC, with no vacancy at the bonded interface in TEM images.

Original language	English
Title of host publication	Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Number of pages	1
ISBN (Electronic)	9784904743034
DOIs	https://doi.org/10.23919/LTB-3D.2017.7947446
Publication status	Published - 2017 Jun 13
Event	5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017 - Tokyo, Japan Duration: 2017 May 16 → 2017 May 18

Publication series

Name	Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017

Other

Other	5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017
Country/Territory	Japan
City	Tokyo
Period	17/5/16 → 17/5/18

ASJC Scopus subject areas

Electrical and Electronic Engineering
Industrial and Manufacturing Engineering
Electronic, Optical and Magnetic Materials
Surfaces, Coatings and Films

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10.23919/LTB-3D.2017.7947446

Cite this

Uomoto, M., Yamada, Y., Hoshi, T., Nada, M., & Shimatsu, T. (2017). Room temperature bonding of InGaAs wafers using thin Ge films. In Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017 [7947446] (Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/LTB-3D.2017.7947446

Room temperature bonding of InGaAs wafers using thin Ge films. / Uomoto, M.; Yamada, Y.; Hoshi, T. et al.
Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7947446 (Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Uomoto, M, Yamada, Y, Hoshi, T, Nada, M & Shimatsu, T 2017, Room temperature bonding of InGaAs wafers using thin Ge films. in Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017., 7947446, Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017, Institute of Electrical and Electronics Engineers Inc., 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017, Tokyo, Japan, 17/5/16. https://doi.org/10.23919/LTB-3D.2017.7947446

Uomoto M, Yamada Y, Hoshi T, Nada M, Shimatsu T. Room temperature bonding of InGaAs wafers using thin Ge films. In Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7947446. (Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017). doi: 10.23919/LTB-3D.2017.7947446

Uomoto, M. ; Yamada, Y. ; Hoshi, T. et al. / Room temperature bonding of InGaAs wafers using thin Ge films. Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017).

@inproceedings{f71c3b5b01ed480f9c579c51eb8e6985,

title = "Room temperature bonding of InGaAs wafers using thin Ge films",

abstract = "Room temperature bonding of InGaAs wafers using thin Ge films was studied. Wafers were bonded even with 0.5 nm thick Ge film on each side. Bonded wafers showed strong bonding force after annealing at 340 oC, with no vacancy at the bonded interface in TEM images.",

author = "M. Uomoto and Y. Yamada and T. Hoshi and M. Nada and T. Shimatsu",

year = "2017",

month = jun,

day = "13",

doi = "10.23919/LTB-3D.2017.7947446",

language = "English",

series = "Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017",

note = "5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017 ; Conference date: 16-05-2017 Through 18-05-2017",

}

TY - GEN

T1 - Room temperature bonding of InGaAs wafers using thin Ge films

AU - Uomoto, M.

AU - Yamada, Y.

AU - Hoshi, T.

AU - Nada, M.

AU - Shimatsu, T.

PY - 2017/6/13

Y1 - 2017/6/13

N2 - Room temperature bonding of InGaAs wafers using thin Ge films was studied. Wafers were bonded even with 0.5 nm thick Ge film on each side. Bonded wafers showed strong bonding force after annealing at 340 oC, with no vacancy at the bonded interface in TEM images.

AB - Room temperature bonding of InGaAs wafers using thin Ge films was studied. Wafers were bonded even with 0.5 nm thick Ge film on each side. Bonded wafers showed strong bonding force after annealing at 340 oC, with no vacancy at the bonded interface in TEM images.

UR - http://www.scopus.com/inward/record.url?scp=85022185000&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85022185000&partnerID=8YFLogxK

U2 - 10.23919/LTB-3D.2017.7947446

DO - 10.23919/LTB-3D.2017.7947446

M3 - Conference contribution

AN - SCOPUS:85022185000

T3 - Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017

BT - Proceedings of 2017 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2017

Y2 - 16 May 2017 through 18 May 2017

ER -

Room temperature bonding of InGaAs wafers using thin Ge films

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