Rule-programmable multiple-valued matching VLSI processor for real-time rule-based systems

Takahiro Hanyu, Koichi Takeda, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


This paper presents a design of a new multiple-valued matching VLSI processor for high-speed reasoning. It is useful in the application for real-time rule-based systems with large knowledge bases which are programmable. In order to realize high-speed reasoning, the matching VLSI processor can perform the fully parallel pattern matching between an input data and rules. On the based of direct multiple-valued encoding of each attribute in an input data and rules, pattern matching can be described by using only a programmable delta literal. Moreover, the programmable delta literal circuit can be easily implemented using two kinds of floating-gate MOS devices whose threshold voltages are controllable. In fact, it is demonstrated that four kinds of threshold voltages in a practical floating-gate MOS device can be easily programmable by appropriately controlling the gate, the drain and the source voltage. Finally, the inference time of the quaternary matching VLSI processor with 256 rules and conflict resolution circuits is estimated at about 360 (ns), and the chip area is reduced to about 30 percent, in comparison with the equivalent binary implementation.

Original languageEnglish
Pages (from-to)472-479
Number of pages8
JournalIEICE Transactions on Electronics
Issue number3
Publication statusPublished - 1993 Mar


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