Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM

T. Tanaka; E. Yoshida; T. Miyashita

Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM

T. Tanaka, E. Yoshida, T. Miyashita

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper describes both operation principle and scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading part among other memories.

Original language	English
Pages (from-to)	919-922
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
Publication status	Published - 2004
Externally published	Yes
Event	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States Duration: 2004 Dec 13 → 2004 Dec 15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM",

abstract = "This paper describes both operation principle and scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading part among other memories.",

author = "T. Tanaka and E. Yoshida and T. Miyashita",

note = "Funding Information: The authors would like to thank M. Matsumiya and S. Eto for their fruitful discussions, and M. Kase and J. Sakuma for device fabrication.; IEEE International Electron Devices Meeting, 2004 IEDM ; Conference date: 13-12-2004 Through 15-12-2004",

year = "2004",

language = "English",

pages = "919--922",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - Scalability study on a capacitorless 1T-DRAM

T2 - IEEE International Electron Devices Meeting, 2004 IEDM

AU - Tanaka, T.

AU - Yoshida, E.

AU - Miyashita, T.

N1 - Funding Information: The authors would like to thank M. Matsumiya and S. Eto for their fruitful discussions, and M. Kase and J. Sakuma for device fabrication.

PY - 2004

Y1 - 2004

N2 - This paper describes both operation principle and scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading part among other memories.

AB - This paper describes both operation principle and scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading part among other memories.

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UR - http://www.scopus.com/inward/citedby.url?scp=21644432584&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:21644432584

SN - 0163-1918

SP - 919

EP - 922

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

Y2 - 13 December 2004 through 15 December 2004

ER -

Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM

Abstract

ASJC Scopus subject areas

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