Scalable 3D-FPGA using wafer-to-wafer TSV interconnect of 15 Tbps/W, 3.3 Tbps/mm2

Futoshi Furuta, Tadayuki Matsumura, Kenichi Osada, Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda, Naoto Miyamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A 'scalable 3D-FPGA' using TSV interconnects is proposed. This FPGA was designed on the basis of homogeneous 3D-stacking to extend the logic scale in proportion to the number of stacked layers. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An 'embedded TSV' design for the shorter on-chip wirings was also devised. Moreover, to reduce the clock skew between the stacked layers arising from global process variations, a 3D clock-synchronization scheme using a reference clock via TSVs was developed. To check connectivity between layers and improves its reliability, test and redundant circuits were embedded into the FPGA. We present the first demonstration of two stacked FPGA layers by using wafer-to-wafer via-last Cu-TSV process. Z-axis transmission performance was the highest, namely, 15 Tbps/W and 3.3 Tbps/mm2. The clock skew between two layers was reduced by 60% using the new clock scheme.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Publication statusPublished - 2013
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 2013 Jun 122013 Jun 14

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Other2013 Symposium on VLSI Circuits, VLSIC 2013


  • 3D
  • FPGA
  • Homogeneous
  • TSV

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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