Tsunehachi Ishitani, Kazuo Tansho, Norio Miyahara, Shuji Kubota, Shuzo Kato

Research output: Contribution to journalArticlepeer-review

25 Citations (Scopus)


A high-speed Viterbi decoder VLSI with coding rate R equals 1/2 and constraint length K equals 7 for bit-error correction has been developed using 1. 5 mu m n-well CMOS technology. To reduce both hardware size and power dissipation, a recently developed scarce-state-transition (SST) Viterbi decoding scheme has been utilized. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9. 52 multiplied by 10. 0 mm**2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mb/s with a net coding gain of 4. 4 dB (at 10** minus **4 bit-error rate). The chip dissipates only 825 mW at a data rate of 10 Mb/s.

Original languageEnglish
Pages (from-to)575-582
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Issue number4
Publication statusPublished - 1987 Aug

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION.'. Together they form a unique fingerprint.

Cite this