Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm

K. Kakushima; K. Okamoto; T. Koyanagi; K. Tachi; M. Kouda; T. Kawanago; J. Song; P. Ahmet; K. Tsutsui; N. Sugii; T. Hattori; H. Lwai

doi:10.1109/ESSDERC.2009.5331331

Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm

K. Kakushima, K. Okamoto, T. Koyanagi, K. Tachi, M. Kouda, T. Kawanago, J. Song, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Lwai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

An aggressive EOT scaling with high-k gate dielectrics has been presented by selection of a rare earth silicate (La, Ce and Pr) as an interfacial layer with La₂O₃ stacking. Among silicates, La₂O ₃/Ce-silicate nFET has performed a small EOT of 0.51 nm with a reduced gate leakage current of 10² A/cm². SrO capping further reduces the gate leakage current also with a smaller EOT with improved subthreshold slope. A guideline for EOT scaling using RE-silicate in combination with SrO capping is proposed.

Original language	English
Title of host publication	ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
Pages	403-406
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDERC.2009.5331331
Publication status	Published - 2009 Dec 1
Event	39th European Solid-State Device Research Conference, ESSDERC 2009 - Athens, Greece Duration: 2009 Sept 14 → 2009 Sept 18

Publication series

Name	ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

Other

Other	39th European Solid-State Device Research Conference, ESSDERC 2009
Country/Territory	Greece
City	Athens
Period	09/9/14 → 09/9/18

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety Research

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10.1109/ESSDERC.2009.5331331

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Kakushima, K., Okamoto, K., Koyanagi, T., Tachi, K., Kouda, M., Kawanago, T., Song, J., Ahmet, P., Tsutsui, K., Sugii, N., Hattori, T., & Lwai, H. (2009). Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm. In ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference (pp. 403-406). [5331331] (ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference). https://doi.org/10.1109/ESSDERC.2009.5331331

Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm. / Kakushima, K.; Okamoto, K.; Koyanagi, T. et al.

ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference. 2009. p. 403-406 5331331 (ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kakushima, K, Okamoto, K, Koyanagi, T, Tachi, K, Kouda, M, Kawanago, T, Song, J, Ahmet, P, Tsutsui, K, Sugii, N, Hattori, T & Lwai, H 2009, Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm. in ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference., 5331331, ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, pp. 403-406, 39th European Solid-State Device Research Conference, ESSDERC 2009, Athens, Greece, 09/9/14. https://doi.org/10.1109/ESSDERC.2009.5331331

Kakushima K, Okamoto K, Koyanagi T, Tachi K, Kouda M, Kawanago T et al. Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm. In ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference. 2009. p. 403-406. 5331331. (ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference). doi: 10.1109/ESSDERC.2009.5331331

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abstract = "An aggressive EOT scaling with high-k gate dielectrics has been presented by selection of a rare earth silicate (La, Ce and Pr) as an interfacial layer with La2O3 stacking. Among silicates, La2O 3/Ce-silicate nFET has performed a small EOT of 0.51 nm with a reduced gate leakage current of 102 A/cm2. SrO capping further reduces the gate leakage current also with a smaller EOT with improved subthreshold slope. A guideline for EOT scaling using RE-silicate in combination with SrO capping is proposed.",

author = "K. Kakushima and K. Okamoto and T. Koyanagi and K. Tachi and M. Kouda and T. Kawanago and J. Song and P. Ahmet and K. Tsutsui and N. Sugii and T. Hattori and H. Lwai",

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AU - Kouda, M.

AU - Kawanago, T.

AU - Song, J.

AU - Ahmet, P.

AU - Tsutsui, K.

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AB - An aggressive EOT scaling with high-k gate dielectrics has been presented by selection of a rare earth silicate (La, Ce and Pr) as an interfacial layer with La2O3 stacking. Among silicates, La2O 3/Ce-silicate nFET has performed a small EOT of 0.51 nm with a reduced gate leakage current of 102 A/cm2. SrO capping further reduces the gate leakage current also with a smaller EOT with improved subthreshold slope. A guideline for EOT scaling using RE-silicate in combination with SrO capping is proposed.

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Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm

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