Simulation study of short-channel effects of tunnel field-effect transistors

Koichi Fukuda, Hidehiro Asai, Junichi Hattori, Takahiro Mori, Yukinori Morita, Wataru Mizubayashi, Meishoku Masahara, Shinji Migita, Hiroyuki Ota, Kazuhiro Endo, Takashi Matsukawa

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal-oxide-semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3nm for single-gate structures and 2nm for double gate structures, as determined from the drain offset structure.

Original languageEnglish
Article number04FD04
JournalJapanese Journal of Applied Physics
Issue number4
Publication statusPublished - 2018 Apr


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