TY - JOUR
T1 - SPA against an FPGA-B ased RSA implementation with a high-radix montgomery multiplier
AU - Miyamoto, Atsushi
AU - Homma, Naofumi
AU - Aoki, Takafumi
AU - Satoh, Akashi
PY - 2007
Y1 - 2007
N2 - Simple Power Analysis (SPA) was applied to an RSA processor with a high-radix Montgomery multiplier on an FPGA platform, and the different characteristics of power waveforms caused by two types of multiplier (built-in and custom) were investigated in detail. We also applied an active attack where input data was set to a specific pattern to control the modular multiplication. The power dissipation for the multiplication was greatly reduced in comparison with modular squaring, resulting in success in revealing all of the secret key bits.
AB - Simple Power Analysis (SPA) was applied to an RSA processor with a high-radix Montgomery multiplier on an FPGA platform, and the different characteristics of power waveforms caused by two types of multiplier (built-in and custom) were investigated in detail. We also applied an active attack where input data was set to a specific pattern to control the modular multiplication. The power dissipation for the multiplication was greatly reduced in comparison with modular squaring, resulting in success in revealing all of the secret key bits.
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U2 - 10.1109/iscas.2007.378274
DO - 10.1109/iscas.2007.378274
M3 - Conference article
AN - SCOPUS:34548827386
SN - 0271-4310
SP - 1847
EP - 1850
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 4253021
T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
Y2 - 27 May 2007 through 30 May 2007
ER -