Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

Takahiro Hanyu; Daisuke Suzuki; Naoya Onizawa; Shoun Matsunaga; Masanori Natsui; Akira Mochizuki

doi:10.7873/date.2015.1119

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki

RIEC - Computing System Platforms Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

21 Citations (Scopus)

Abstract

Novel logic-LSI architecture, called 'spintronics-based nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile spintronic storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic-LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

Original language	English
Title of host publication	Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1006-1011
Number of pages	6
ISBN (Electronic)	9783981537048
DOIs	https://doi.org/10.7873/date.2015.1119
Publication status	Published - 2015 Apr 22
Event	2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France Duration: 2015 Mar 9 → 2015 Mar 13

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE
Volume	2015-April
ISSN (Print)	1530-1591

Conference

Conference	2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Country/Territory	France
City	Grenoble
Period	15/3/9 → 15/3/13

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10.7873/date.2015.1119

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Hanyu, T., Suzuki, D., Onizawa, N., Matsunaga, S., Natsui, M., & Mochizuki, A. (2015). Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 (pp. 1006-1011). Article 7092537 (Proceedings -Design, Automation and Test in Europe, DATE; Vol. 2015-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/date.2015.1119

Hanyu, Takahiro ; Suzuki, Daisuke ; Onizawa, Naoya et al. / Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1006-1011 (Proceedings -Design, Automation and Test in Europe, DATE).

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abstract = "Novel logic-LSI architecture, called 'spintronics-based nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile spintronic storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic-LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.",

author = "Takahiro Hanyu and Daisuke Suzuki and Naoya Onizawa and Shoun Matsunaga and Masanori Natsui and Akira Mochizuki",

note = "Publisher Copyright: {\textcopyright} 2015 EDAA.; 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 ; Conference date: 09-03-2015 Through 13-03-2015",

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doi = "10.7873/date.2015.1119",

language = "English",

series = "Proceedings -Design, Automation and Test in Europe, DATE",

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Hanyu, T, Suzuki, D, Onizawa, N, Matsunaga, S, Natsui, M & Mochizuki, A 2015, Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015., 7092537, Proceedings -Design, Automation and Test in Europe, DATE, vol. 2015-April, Institute of Electrical and Electronics Engineers Inc., pp. 1006-1011, 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015, Grenoble, France, 15/3/9. https://doi.org/10.7873/date.2015.1119

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. / Hanyu, Takahiro; Suzuki, Daisuke; Onizawa, Naoya et al.
Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1006-1011 7092537 (Proceedings -Design, Automation and Test in Europe, DATE; Vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Natsui, Masanori

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AB - Novel logic-LSI architecture, called 'spintronics-based nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile spintronic storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic-LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

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Hanyu T, Suzuki D, Onizawa N, Matsunaga S, Natsui M, Mochizuki A. Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1006-1011. 7092537. (Proceedings -Design, Automation and Test in Europe, DATE). doi: 10.7873/date.2015.1119

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

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