TY - GEN
T1 - SPRAM (SPin-transfer torque RAM) design and its impact on digital systems
AU - Kawahara, T.
AU - Takemura, R.
AU - Takahashi, H.
AU - Ohno, Hideo
PY - 2007/12/1
Y1 - 2007/12/1
N2 - To demonstrate circuit technologies for potential low-power non-volatile RAM, or universal memory, we fabricated a 1.8V 2-Mb SPRAM (SPin-transfer torque RAM) chip using a 0.2-μm logic process with a MgO tunneling barrier cell. This chip features an array scheme with bit-by-bit bidirectional current writing to enable proper spin-transfer torque writing and parallel-direction current reading for preventing read disturbance. In addition, this memory can improve the power efficiency of digital equipment.
AB - To demonstrate circuit technologies for potential low-power non-volatile RAM, or universal memory, we fabricated a 1.8V 2-Mb SPRAM (SPin-transfer torque RAM) chip using a 0.2-μm logic process with a MgO tunneling barrier cell. This chip features an array scheme with bit-by-bit bidirectional current writing to enable proper spin-transfer torque writing and parallel-direction current reading for preventing read disturbance. In addition, this memory can improve the power efficiency of digital equipment.
UR - http://www.scopus.com/inward/record.url?scp=50649107685&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=50649107685&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2007.4511164
DO - 10.1109/ICECS.2007.4511164
M3 - Conference contribution
AN - SCOPUS:50649107685
SN - 1424413788
SN - 9781424413782
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 1011
EP - 1014
BT - ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Y2 - 11 December 2007 through 14 December 2007
ER -