TY - GEN
T1 - Stacked SOI pixel detector using versatile fine pitch μ-bump technology
AU - Motoyoshi, Makoto
AU - Takanohashi, Junichi
AU - Fukushima, Takafumi
AU - Arai, Yasuo
AU - Koyanagi, Mitsumasa
PY - 2011
Y1 - 2011
N2 - This Paper presents on 3D stacking technology with 2.5μm x 2.5μm In (Indium) bump connections with adhesive injection [1]. Instead of using the simple test device, this technology has been verified using the actual circuit level test chip. And it was found that the completion of stacking process is affected by the layout pattern of stacked each tier. In order to minimize those effects, we have optimized the layout, process parameter and device structure.
AB - This Paper presents on 3D stacking technology with 2.5μm x 2.5μm In (Indium) bump connections with adhesive injection [1]. Instead of using the simple test device, this technology has been verified using the actual circuit level test chip. And it was found that the completion of stacking process is affected by the layout pattern of stacked each tier. In order to minimize those effects, we have optimized the layout, process parameter and device structure.
UR - http://www.scopus.com/inward/record.url?scp=84866864006&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84866864006&partnerID=8YFLogxK
U2 - 10.1109/3DIC.2012.6262959
DO - 10.1109/3DIC.2012.6262959
M3 - Conference contribution
AN - SCOPUS:84866864006
SN - 9781467321891
T3 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
BT - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
T2 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Y2 - 31 January 2012 through 2 February 2012
ER -