Statistical p-n junction leakage model via trap level fluctuation for refresh-time-oriented dynamic random access memory design

We have developed a new model for the leakage current of a single tail bit of dynamic random access memories (DRAMs). This model can explain the leakage current of each tail bit quantitatively. To derive model equations, we assume that some bits containing one specific trap center become tail bits among all bits in a DRAM chip. The variation of the leakage current of tail bits is attributed to the fluctuation of the trap level. Extracted value of the average trap level is 0.677 eV, which is the close value of the trap centers generated by Cu and Fe. By introducing the trap level fluctuation model, we have successfully reproduced the distribution of the retention time for tail bits. We also have obtained a good agreement between model and experimental results of tail distributions as functions of process splits and the temperature by using the present model. As an example applied by the present model, we estimated the required number of the repairable bits for 1 Gbyte DRAM.