TY - GEN
T1 - Stochastic implementation of the disparity energy model for depth perception
AU - Boga, Kaushik
AU - Onizawa, Naoya
AU - Leduc-Primeau, François
AU - Matsumiya, Kazumichi
AU - Hanyu, Takahiro
AU - Gross, Warren J.
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/12/2
Y1 - 2015/12/2
N2 - We implement a binocular vision system based on a disparity-energy model that emulates the hierarchical multi-layered neural structure in the primary visual cortex. Layer 1 performs difference-of-Gaussian filtering that mimicks the center-surround receptive fields (RF) in the retina, layer 2 performs Gabor filtering mimicking the orientation selective filtering performed by simple cells and layer 3 has complex cells tuned to detecting 5 different disparities. A VLSI architecture is developed based on stochastic computing that is compact and adder-free. Even with a short stream length, the proposed architecture achieves better disparity detection than a floating-point version by using a modified disparity-energy model. A 1 × 100 pixel processing system is synthesized using TSMC 65nm CMOS technology and achieves up to 79% reduction in area-delay product compared to a fixed point implementation.
AB - We implement a binocular vision system based on a disparity-energy model that emulates the hierarchical multi-layered neural structure in the primary visual cortex. Layer 1 performs difference-of-Gaussian filtering that mimicks the center-surround receptive fields (RF) in the retina, layer 2 performs Gabor filtering mimicking the orientation selective filtering performed by simple cells and layer 3 has complex cells tuned to detecting 5 different disparities. A VLSI architecture is developed based on stochastic computing that is compact and adder-free. Even with a short stream length, the proposed architecture achieves better disparity detection than a floating-point version by using a modified disparity-energy model. A 1 × 100 pixel processing system is synthesized using TSMC 65nm CMOS technology and achieves up to 79% reduction in area-delay product compared to a fixed point implementation.
UR - http://www.scopus.com/inward/record.url?scp=84958231263&partnerID=8YFLogxK
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U2 - 10.1109/SiPS.2015.7344982
DO - 10.1109/SiPS.2015.7344982
M3 - Conference contribution
AN - SCOPUS:84958231263
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
BT - Electronic Proceedings of the 2015 IEEE International Workshop on Signal Processing Systems, SiPS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Workshop on Signal Processing Systems, SiPS 2015
Y2 - 14 October 2015 through 16 October 2015
ER -