Structural design of three-dimensionally stacked silicon chips for minimizing their residual stress

Since mechanical stress sometimes degrades both electronic functions and reliability of LSI chips, it is very important to control the residual stress in them to assure their highly reliable performance. The authors have already found that the local residual stress distribution on the transistor formation surface of LSIs changes significantly depending on their assembly structure. In addition, we have found that the dominant structural factors that determine the distribution are the thickness of a chip, thermal expansion coefficient of underfill material and the shape and the relative position of bumps among stacked chips. In this study, we proposed the optimum stacked structures for minimizing the residual stress based on a finite element analysis. When the thickness of the upper and bottom chips are thinned from 100 um to 30 μm, the average value of the normal stress increased monotonically regardless of the material of a substrate. The rate of the increase of the average value was about 0.6 MPa/μm when the material of the substrate was silicon, while the rate of the increase was about 2.0 MPa/μm when the substrate was an organic one. On the other hand, the maximum amplitude of the normal stress in the both chips mounted on an organic substrate was decreased to about 0 MPa, while the maximum amplitude of the normal stress in the stacked chips mounted on a Si substrate changed complicatedly. Therefore, it can be said that a Si substrate is effective for minimizing the increase of the average vale of the normal stress, while an organic substrate is effective for minimizing the maximum amplitude of the normal stress by thinning of the chip. But, it was also found that there was no way to decrease both the average stress and the maximum amplitude of the residual stress at the same time. It is very important, therefore, to optimize the structure of each product by considering the most important part of the stress that dominates the electronic performance of the product. However, it should be also noted that the thermal residual stress in the whole structure can not be made 0 because there is the difference of material properties among LSI chips, bumps, underfill and substrates. Thus, the stress sensitivity of electronic performance and reliability of each chip should be evaluated before this structural design.