This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-μm GaAs MESFET technology.
|Number of pages||4|
|Publication status||Published - 1996|
|Event||Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Orlando, FL, USA|
Duration: 1996 Nov 3 → 1996 Nov 6
|Conference||Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium|
|City||Orlando, FL, USA|
|Period||96/11/3 → 96/11/6|