Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs

Taiichi Otsuji; Mikio Yoneyama; Koichi Murata; Eiichi Sano

Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs

Taiichi Otsuji, Mikio Yoneyama, Koichi Murata, Eiichi Sano

RIEC - Information Communication Platforms Division

Nippon Telegraph & Telephone

Research output: Contribution to conference › Paper › peer-review

21 Citations (Scopus)

Abstract

This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-μm GaAs MESFET technology.

Original language	English
Pages	145-148
Number of pages	4
Publication status	Published - 1996
Event	Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Orlando, FL, USA Duration: 1996 Nov 3 → 1996 Nov 6

Conference

Conference	Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
City	Orlando, FL, USA
Period	96/11/3 → 96/11/6

Cite this

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title = "Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs",

abstract = "This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-μm GaAs MESFET technology.",

author = "Taiichi Otsuji and Mikio Yoneyama and Koichi Murata and Eiichi Sano",

year = "1996",

language = "English",

pages = "145--148",

note = "Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium ; Conference date: 03-11-1996 Through 06-11-1996",

}

Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs. / Otsuji, Taiichi; Yoneyama, Mikio; Murata, Koichi et al.
1996. 145-148 Paper presented at Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, Orlando, FL, USA.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs

AU - Otsuji, Taiichi

AU - Yoneyama, Mikio

AU - Murata, Koichi

AU - Sano, Eiichi

PY - 1996

Y1 - 1996

N2 - This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-μm GaAs MESFET technology.

AB - This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-μm GaAs MESFET technology.

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M3 - Paper

AN - SCOPUS:0030405059

SP - 145

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T2 - Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium

Y2 - 3 November 1996 through 6 November 1996

ER -

Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs

Abstract

Conference

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